New Breed of Low-Noise Integrated VCO/PLL RF-Synthesizers Suits Wireless Infrastructure

By Matthias Feulner, Texas Instruments

Business Development Manager Wireless Infrastructure

Synthesizers in Wireless Communications

In wireless communications system design the synthesizer generating the local oscillator (LO) clock for the mixers and (de-) modulators is one of the critical components determining system performance. Its imperfections will directly reduce system margin and thus impact sensitivity in the receiver and Error Vector Magnitude (EVM) as well as signal spectral properties in the transmitter. Representing the typical application, a wireless transceiver configuration using a heterodyne (dual-conversion) diversity receiver and a direct-conversion transmitter is shown in Figure 1.

Figure 1: Wireless base station transceiver

Synthesizer Parameters Affecting System Performance

For illustrating system impact of synthesizer performance we will look at a receiver implementation, similar considerations can be applied for the transmitter. Underlying standards, for example 3GPP standard for GSM [1], specify receiver sensitivity and required tolerance with respect to interferer signals. These are typically mobile handsets or base stations transmitting on another frequency with potentially much larger signal power than the desired signal present at the receiver. While at the down-conversion mixer the desired signal is mixing with the LO to generate a useful signal at an intermediate frequency (IF), the interferer may be mixing with the LO's phase noise and spurs thus generating interference at the signal frequency, effectively reducing signal to noise ratio. Cause and effect of these distortions can be explained by taking a look at a standard synthesizer implementation [3]:

Figure 2: Synthesizer with integer-N PLL and external VCO [3]

The implementation of a so-called integer-N Phase Locked Loop (PLL) synthesizer in Figure 2 compares a low reference input frequency f_ref with the output frequency f_VCO of a high-frequency VCO. This takes place in the so-called Phase Frequency Detector (PFD). To match both frequencies, which may by differing by factors of up to 200 and more, the input frequency is divided down by a factor of R, the VCO frequency by a factor of N, which results in a comparison frequency f_PFD at the PFD. The PFD will compare divided-down frequencies from the input and VCO and generate a control signal to increase or decrease VCO frequency until both inputs of the PFD circuit are equal. This is when the PLL is said to be locked.

Synthesizer Phase Noise

Ideally the LO synthesizer would generate only one discrete frequency, but in reality this is not the case and the synthesizer output spectrum contains in addition a broadband noise contribution, the so-called phase noise.

Several possible sources of noise contribute to this: Phase noise by the VCO itself, noise introduced by the dividers of the PLL, noise due to loop filter components, etc. Due to filtering characteristics of the PLL circuitry and particularly the (low-pass) loop filter inside the filter's loop bandwidth noise will be dominated by PLL itself, outside the loop bandwidth by the phase noise of the VCO.

The presence of phase noise from the LO at the receiver's down-conversion mixer now may cause mixing of a potential interferer signal with the wideband phase noise, creating interference at the signal frequency at the mixer output as shown in Figure 3. With interferer signals potentially much larger than the desired signal there is a risk of masking the desired signal after down-conversion to IF.

Figure 3: Synthesizer phase noise mixing with interferer

Synthesizer Spurs

When the PLL is in lock theoretically the PFD would not output any control signal to change VCO frequency. Practically it will be generating short alternating current pulses at a rate equal to f_PFD that on average are supposed to keep the output frequency constant. In case these alternating pulses are not perfectly matched this will give rise to discrete spurious signals present at the synthesizer output at offsets from the center frequency which are multiples of f_PFD. Unfortunately f_PFD with integer-N PLLs usually needs to be chosen to coincide with the channel spacing of the system (i.e. 200 kHz in GSM) which results in mixing products between the spurious signals and the signal itself as well as possible interferers. Mixing of the spurious with interferer signals in the receiver may again create interference at the signal frequency after down-conversion to the IF. In the transmitter mixing of the signal with the spurious may cause interference at other frequencies thus potentially violating output spectrum modulation mask requirements. The effect is illustrated for the receiver in Figure 4.

Figure 4: Synthesizer spurious components mixing with interferer signal in receiver

System Requirements

As explained both phase noise and spurs mixing with the signal by itself or interferers may create undesired interference with signal channels, effectively reducing signal to noise ratio and ultimately limiting receiver sensitivity. To ensure proper operation in a GSM system, the requirements set by the 3GPP standard have to be met. These are:

- Receiver reference sensitivity

- Blocking characteristics

- Interference (carrier-to-interferer) ratio and intermodulation

This allows deriving the relevant specifications for the receive synthesizer. For the phase noise, assuming a desired signal level of -101dBm and a carrier to interference ratio of 9dB this results in following requirements [1,2]:

Offset from carrier	GSM400 & GSM900		DCS1800 & PCS1900
	Integrated wide-band noise in 200kHz bandwidth	Equivalent Phase Noise	Integrated wide-band noise in 200kHz bandwidth	Equivalent Phase Noise
600 kHz ≤ │f-fo│ < 800 kHz	-84 dBc	-137 dBc/Hz	-75 dBc	-128 dBc/Hz
800 kHz ≤ │f-fo│ < 1.6 MHz	-94 dBc	-147 dBc/Hz	-85 dBc	-138 dBc/Hz
1.6 MHz ≤ │f-fo│ < 3 MHz	-94 dBc	-147 dBc/Hz	-85 dBc	-138 dBc/Hz
3 MHz ≤ │f-fo│	-97 dBc	-150 dBc/Hz	-85 dBc	-138 dBc/Hz

Table 1: Wideband noise and phase noise requirements for GSM Rx synthesizer

The ‘integrated wide-band noise' requirement combines the effects of both phase noise and spurs within the 200kHz channel bandwidth since they both result in similar effects on receiver sensitivity. Considerations for the transmitter are somewhat different, specifying effects due to ‘wideband noise and modulation  mask' to prevent interference of the transmit channel with possibly present neighbouring channels from other base stations.

Traditional Implementations and Integrated Solutions

Meeting the phase noise and spurs requirements for GSM systems has always been a challenge and the VCO, PLL and loop filter that build the synthesizer had to be optimized carefully. Implementations with discrete VCOs, usually laser-trimmed for frequency accuracy, and high-performance integer-N PLLs like Texas Instruments' TRF3750 made it possible to build synthesizer's complying with the stringent requirements.

Taking that approach one step further, to reduce foot-print, cost and design complexity the concept of integrated VCO/PLL synthesizers has been pursued for quite some time already and is nowadays pretty much standard particularly in handset implementations. But the very stringent requirements of wireless infrastructure equipment, GSM being particularly challenging, have for a long time prevented use of this convenient concept in base stations. Now recent advances in integrated device performance have made it possible to extend their usage into infrastructure applications. The integrated integer-N VCO/PLL TRF3761 from Texas Instruments is the first of this new breed of high performance integrated VCO/PLLs. It is a fully integrated integer-N PLL with on-chip VCO as shown in Figure 5 [4]. Additionally a built-in output divider allows operation at half and quarter of the VCO frequency thus extending operating range. Among the few external components required to turn this into a complete synthesizer is the loop filter which in turn allows for more flexibility in optimizing overall synthesizer performance.

Figure 5: Integrated VCO/PLL synthesizer functional block diagram

As explained before, phase noise and spurs are critical performance parameters and to examine performance of the device we take a closer look at the phase noise plots including spurs of a synthesizer with f_VCO set to 1800MHz. Loop filter in this case was designed to be 15kHz, the device's PFD is operating at 200kHz while a reference frequency of 10MHz was input to the device. By using different output divider ratios we as well obtain the results from a 900MHz and a 450MHz output signal.

Figure 6: TRF3761 phase noise at f_out = f_VCO = 1800MHz

Figure 7: TRF3761 phase noise at f_out = f_VCO / 2 = 900MHz

Figure 8: TRF3761 phase noise at f_out = f_VCO / 4 = 450MHz

Comparing the plots with requirements given in Table 1 confirms that requirements for a GSM Rx synthesizer in the 400MHz, 900MHz and 1800/1900MHz bands can be met both for phase noise as well as integrated wide-band noise (including spurs) under the conditions stated there. At the same time this qualifies such class of device readily for operation in 3G wireless systems like WCDMA and CDMA2000 as well as Wireless Broadband and emerging applications like 802.16 which impose less demanding requirements.

References:

[1] 3GPP TS 05.05 V8.20.0 (2005-11)

[2] GSM transceiver analysis, Heinz-Peters Beckemeyer, Texas Instruments

[3] TRF3750 data sheet: http://focus.ti.com/docs/prod/folders/print/trf3750.html

[4] TRF3761 data sheet: http://focus.ti.com/docs/prod/folders/print/trf3761.html