New Serial Interface Standard for High Speed Data Converters Set to Reduce Design Complexity & Cost, Enhance Performance


By Matthias Feulner, Texas Instruments

Business Development Manager Wireless Infrastructure

Why Go Serial?

Serializing output data of high-speed analog-to-digital converters is a relatively new concept, even though first generation devices have been around for a couple of years now. The demand for changing from parallel to serial output format was primarily driven by high-density applications such as medical imaging, for example in ultra-sound scanners (see Figure 1),  with channel counts reaching up to 256 channels per equipment as well as  wireless radio base station receiver architectures in diversity or smart-antenna configurations that employ IQ sampling, requiring two AD converters per receiver chain (see Figure 2).

 

 

Figure 1: Medical ultrasound scanner receiver signal chain

 

 

Figure 2: Wireless base station Rx with I/Q sampling in diversity (n=2) / smart antenna configuration

 

Today's Serial Interface Implementations

 

Most of today's commercially available flavors of serial output (high-speed) AD converters are based on the so-called ‘clock-data-frame' interface, illustrated in Figure 3 with the example of an octal 12bit  AD converter, that outputs on individual lines:

 

  • serialized digital sampling data
  • bit clock, which is 6x the ADC sampling clock frequency, to clock the serial interface in DDR mode both on the falling and rising edge
  • frame synchronization clock, which is identical with the ADC sampling clock frequency to signal the data word boundary for the receiving device

 

 

 

Figure 3: Serial AD converter with clock-data-frame output interface [1]

 

The electrical interface is based on low-voltage differential signaling (LVDS), a low-swing differential interface that allows for low-power driver implementation, limits electro-magnetic emissions and is highly interference tolerant.

 

Limitations of this interface are on maximum data throughput, which with LVDS is commonly limited to about 1 Gigabits per second (Gbps), reach (limited by skew between clock and data lines) and lack of compatibility with standardized serial interfaces.

JEDEC Interface Standardization and its Advantages

Overview

 

Now a new standard for a serial interface connecting (high-speed) data converters with logic devices such as ASICs and FPGAs has recently passed voting by JEDEC task group JC-16, supported by a large group of both users and manufacturers of data converters and logic devices. Publication of the official standard will follow shortly. The summary of requirements addressed by this standard is as follows:

 

  • Cost-effectiveness, requiring underlying technology to be widely available to both data converter and ASIC / FPGA vendors with no IP hurdles.
  • Serial interface format in order to minimize traces and pin counts.
  • Minimum coding overhead and associated digital logic on the converter to limit added power and noise coupling which are directly affecting the converter's performance.
  • Generally support for data converters with resolutions from 8 to 18 bits which results in gross data rate of 0.3125 – 3.125 Gbps (higher rates can be achieved by multiplexing data across multiple lanes in a future extension of the standard).
  • Optimized for chip-to-chip interconnect, i.e. no cabling or connectors envisioned in the medium (even though a possible future extension).
  • Up to 8" (20 cm) of trace length on FR-4 PCBs or up to 6 dB of loss.
  • Differential and low-swing electrical interface for minimum electromagnetic emissions and high interference tolerance.
  • Common interface regardless of data converter resolution.

 

The generic system view assumed in the standardization considers a very wide variety of possible configurations:

 

  • One converter connected across a single serial link.
  • Multiple converters (in a common package) connected across a single serial link.
  • One converter connected across multiple serial links. (not described in the current version of the standard, but an option for future extension).
  •  

 

Figure 4: AD converter(s) connected to logic device  using JEDEC interface [2, simplified]

 

 

 

Figure 5: Logic device connected to DA converter(s) using JEDEC interface [2, simplified]

 

Electrical Interface

 

The solution that was decided to best meet conditions stated above is an electrical interface similar to the OIF's TFI-5 and SXI-5 specifications, what is commonly referred to as Current Mode Logic (CML). The major advantage of this choice is that numerous other applications have used that interface in the past and thus it is widely supported in the industry, particularly with suppliers of FPGAs and ASICs which readily include compliant interfaces with their standard I/O libraries. On top CML has proven to support data rates of up to 3.125Gbps (as required by the standard) and beyond, drive lines of up to 40 inches and allows for scalable voltage swing to save power in short-reach applications.

Data Stream & Formatting

 

The transport layer protocol is based on 8B10B coding, again a technique that is widely used in serial interface devices with only low overhead adding to the complexity of the device. This ensures both a DC-free line code, i.e. allows for AC coupling with the serial link, and encodes the line clock information with the data stream thus not requiring an additional clock line between transmitter and receiver.

 

Since an 8B10B coding based transport layer encodes data words of 8bit each, any converter output data word aside from 8 or 16 bits does not match up with the word length of the serial link interface. Several measures are taken to ensure that bandwidth efficiency is maximized and crosstalk between serial interface logic and the analog converter circuitry is minimized. First, converter data word packing is applied, i.e. if data converter resolution is other than 8 or 16 bits, data words from multiple converters in the same package may be concatenated as shown in Figure 6, thus avoiding wasting of excess bits.

 

Second, to circumvent the cross-talk issue, the bit and word clocks of the SerDes interface should be an integer multiple of the converter's sampling clock. With word clock to bit clock ratio of 10 defined by the 8B10B coding scheme, one still needs to ensure that word clock and sample clocks are linked by an integer ratio. This is resolved by adding padding bits to fill up the last data word of a data frame transmitted.

 

Figure 6: Word packing and bit padding to fit data from two 14bit converters to 8bit data words [3]

 

Eventually, to ensure that the link is ‘always on', dealing with systems where there isn't a continuous data stream and avoiding issues with re-lock time of the receiver PLL upon link re-start as well as keeping frame format if only one out of multiple converters feeding a data frame is turned off, an idle sequence needs to be sent for the inactive converter(s).

 

As a means of establishing link synchronization during start-up and maintaining frame synchronization during operation a sync signal is being looped back from the receiving device to the sending that triggers certain start-up and link maintenance procedures. More detail can be found in [3].

 

Resulting Benefits

 

The benefits resulting from a JEDEC-based serial interface implementation on data converters are manifold:

 

  • Reduction in board space needed for both data converter package and routing of I/O lines on the board, thus easier layout and potentially a reduction on the number of board layers required
  • Package cost reduction by eliminating I/Os: A particularly heavy-weighing advantage in wireless communications where high-resolution data converters  are being employed and consequently packages of both data converters and logic devices tend to be I/O bound rather than chip-size bound, i.e. the size of the package, and thereby its cost, is dominated by the I/O count rather than the chip size.
  • Longer distances and / or higher through-put can be achieved both compared to parallel interfaces as well as the clock-date-frame serial interface implementation which struggle with skew between data lines themselves and data lines and clock line respectively.
  • High degree of interoperability and thus easy interfacing with commercially available logic devices is enabled by relying on 8B10B coding based transport layer with electrical specifications complying with TFI5/SXI5-like CML-based physical layer.
  • Generic interface, i.e. neither dependent on data converter resolution or sampling speed nor on number of converters integrated in a single package.

 

With the official standard in the publication process at this time, first data converters based on the new interface can be expected to both reduce design complexity and cost and enhance system performance in the near future.

 

References:

 

[1] TI ADS5270 Data Sheet (http://focus.ti.com/docs/prod/folders/print/ads5270.html)

[2] JEDEC Data Converter Serial Interface Specification: Overview

[3] JEDEC Data Converter Serial Interface Specification: Data Stream

[4] OIF Implementation Agreements on TFI5/SXI5 Interfaces at
     www.oiforum.com/public/impagreements.html