Concurrent Circuit/System Design of Digitally
Predistorted Power Amplifiers
Joel Kirshman, & Dr. Michael Heimlich - Applied Wave
Research, Inc.
Introduction
The
critical role of the power amplifier (PA) in both handset and basestation
applications has been well documented. In
order to maintain efficient use of allocated bandwidth, the PA must be operated
in the linear region to ensure that the adjacent channels are not interfered
with. The cost of this, left to its own, is a
power hungry or over-specified PA. Predistortion
techniques (particularly digital predistortion) have
been the preferred method for obtaining needed performance from a less capable
PA.
This paper describes
a more efficient method whereby the circuit- and system-level codesign of digitally predistorted
PAs is executed using co-simulation at the circuit
and system levels. A sub-optimal PA is
used to demonstrate the efficacy of digital predistortion.
The nature of the design tools and the speed at which they simulate are noted.
The result is a more efficient design flow and higher performance PA.
Circuit Design
A commercially available wideband code division multiple
access (WCDMA) PA reference design[1]
is used as a starting point, and the output and input matching networks are
tuned to provide nearly identical power out at the new frequency of interest,
1900MHz. Figure 1 shows the output power
as a function of input power for the original and redesigned PAs at their respective frequency bands. The redesigned PA shown
in Figure 2 can be compared to the original in reference [1].
Figure 1: Pin vs. Pout for Original
and Retargeted Design
The emphasis is not directly on the PA, but on how quickly a
change can be made, the performance re-simulated, and a new behavioral model
extracted and simulated at the system level. Let the total time for this event
be called the codesign delay. The codesign
time would typically be minutes or longer when the circuit simulator and the
system simulator do not share a common object-oriented data model, a common
simulation backplane, or other means for dynamic updating. For example, a symbolic
math tool such as MatLabä, or a
spreadsheet such as Microsoft Excelä at the system level, would be, with
some manual effort, combined with a SPICE-based circuit simulator.
For this system/circuit design, we have used a suite of
tools that supports both system and circuit design with full concurrency
through a common object-oriented runtime data model. In this environment, for
example, the power output performance vs. both frequency and power is displayed
in Figure 3, which shows that the design has not been completely re-centered at
1900MHz from its 2100MHz roots. The codesign time for
a simulation involving a nested power and frequency sweep (from 1600 to
2600MHz) is 20 seconds on a 1.6GHz processor, despite the fact that the PA is
clearly beyond compression and into breakdown. For the same design, the codesign delay for a power sweep alone takes approximately one
second.
In comparison, a SPICE-and-spreadsheet approach can take
from minutes to hours, sometimes with several manual, error-prone steps needed to
implement.
Figure 2: Layout of Redesigned PA
Figure 3: PA Pout (dBm) vs. Pin (dBm) vs. Frequency
(MHz)
System Design
There are several current methods
used in the wireless communications industry to improve the linearity of a PA.
For example, system engineers can select from Cartesian feedback, feedforward error correction, and baseband digital predistortion circuits. The rationale for building such
circuits is to reduce back-off, and, therefore, increase a PA’s efficiency. The
net effect of using these methods is a reduction in adjacent channel leakage
ratio (ACLR) or adjacent channel power ratio (ACPR). While each these methods
has its own merits, digital predistortion is a viable
alternative from an implementation cost and power efficiency perspective.
Baseband digital predistortion
is exactly what it sounds like: digital signal processing (DSP) techniques are
used to predistort the in-phase and quadrature
components of a baseband signal prior to modulation and amplification. The
signal is distorted so as to produce the inverse amplitude (AM/AM) and phase (AM/PM)
characteristics of the PA. From an operating perspective, the digital predistorter adds a gain of 0dB for input power levels in
the linear region of the PA and amplifies or attenuates input power levels in
the nonlinear region of the PA. The overall gain of the digital predistortion network (PDN) in tandem with the PA is
equivalent to the original PA’s gain (G) as shown in Figure 4. In addition, the
PDN introduces a phase shift to the baseband signal that is the inverse of the
PA’s AM/PM characteristic.
Figure 4.
To design a PDN, you first measure a PA’s AM/AM and AM/PM
characteristics. For illustrative
purposes Table 1 shows a “snap shot” of an amplifier’s AM/AM and AM/PM data. Clearly,
the amplifier’s linear gain is approximately 11dB.
Table 1: AM/AM and AM/PM of PA
The next
step is to generate the inverse of the AM/AM and AM/PM characteristics. Note
that the overall gain (G) of the PDN in series with the PA has to be 11dB. To
calculate the PA’s inverse characteristics, we look at two simple examples
using Figure 4 and the data in Table 1 to provide insight on how the inverse characteristics
are derived. In the first example, let the detected input power level (PIN)
of the signal prior to the PDN be -10dBm. With G
set to 11dB, the resulting output power (POUT) is about 1dBm. Thus,
the digital predistorter would apply 0dB of gain to PIN,
and P’ would equal -10. In
the second example, let PIN = -2dBm.
Now, G + PIN = 9. To ensure that the PA outputs 9dBm you can
see from Table 1 that the PDN’s output, P’, would need
to be somewhere between -2dB and 0dB. Determining the exact value of P’
requires a custom algorithm or some form of interpolation. In this example,
linear interpolation was used to calculate a value of -2.002 for P’. Hence, for
PIN= -2 the PDN applies an attenuation of 0.002dB to ensure G = 11dB. You can use a similar exercise to derive the
inverse AM/PM data. The resulting “inverse”
values were calculated as part of the system simulation software as shown in Table
2.
Table 2: Inverse AM/AM and AM/PM of
PA
With the inverse characteristics in hand, we now have to create
a circuit to digitally predistort the baseband signal’s
in-phase (I) and quadrature (Q) components. The
look-up table (LUT) is the essential DSP component of the PDN. The LUT stores
the necessary coefficients to scale the incoming IQ signals; therefore, the
next step is to calculate the individual in-phase PDN coefficients (IiPDN)
and quadrature PDN coefficients (QiPDN) of the LUTs. One
LUT table stores IPDN
values and the other stores QPDN
values. The result of multiplying the incoming IQ signal by corresponding
coefficients effectively scales the baseband signal to ensure an overall 11dB
gain. The following mathematics determine an IiPDN ,QiPDN
pair for each P’ listed in Table 2.
For
example, for PIN = -2dBm, Table 2 shows that P’ = -2.002dBm, the
gain of the digital predistorter is -0.002dB, and the inverse phase is 20.1620.
Therefore, we want IPDN to equal 0.93851 and QPDN to equal 0.3446 to achieve a 0.002dB PDN gain and
an overall 11dB gain. This process can be repeated to calculate an IiPDN ,QiPDN
pair for each P’ value.
Now that we can derive the wanted coefficients for the LUTs, we need to tie everything together. Specifically, we
have to take an incoming IQ pair and multiply it by the appropriate scaling IPDN ,QPDN pair. In this
paper, for simulation purposes the indexing of the LUTs
is governed by PIN. Thus, the power of the IQ signal, PIN,
is calculated and the resulting value is used to pick the correct IPDN ,QPDN pair to predistort the baseband signal.
Figure 4 shows a block diagram of the circuit used to digitally
predistort a 1.2288MHz quadrature phase shift-keying
(QPSK) signal. It depicts the overall circuit of the PDN. The inverse
characteristics of the PA, as well as the LUT’s
coefficients, were derived within seconds using a system simulator.
A circuit is used to calculate the instantaneous output
power of the QPSK source or PIN, PIN is used to select
the appropriate IPDN ,QPDN pair from the LUTs,
the baseband signal is broken into its I and Q components, and a complex
multiple of the original IQ with the corresponding IPDN ,QPDN
pair is performed. Figure 5 shows the complete circuit.
Figure 5: Digital Predistortion Network
Figure 6
shows the resulting improvement in the spectrum as well as the AM/AM
characteristics of the PA and that of the predistortion
network in tandem with the PA.
Clearly,
the digital predistortion network reduced the amount
of spectral regrowth.
Because the LUT table can be calculated in seconds and, for narrow band
operation, circuit-level PA codesign delay is on the
order of seconds (i.e. power sweep only), it is now
practical to make nearly real time trade-offs between system and circuit level
performance and parameters because of a low total codesign
delay.
Figure 6
Power Spectrum and AMtoAM Characteristics
Summary
The ability
to co-simulate the digital predistortion with the
actual embedded PA allows the design flow to consider interactions, design
centering, and robustness in the interaction between the two major
subcomponents. The construction of the digital predistortion
for the PA is highly dependent on the characteristics of the PA, and any
changes in the PA’s performance due to circuit-based considerations require a
redesign of the predistorter. The notion of a “codesign
delay” as a figure of merit is introduced. A tightly-coupled circuit and system
simulation environment with codesign delay on the
order of seconds leads to a concurrent and nearly real time design flow of the
system as a whole regardless of changes at the system or the circuit level. Both
the LUT-based predistorter and the circuit-based PA
simulations have codesign delays of seconds. The
result is a greater freedom to explore the interaction between circuit and
system in complex basestation topologies.
References
[1] MRF21125
WCDMA Reference Design, from Freescale Semiconductor,
Inc.