Supporting Femtocell Baseband Architectures Using Low Cost FPGAs

 

Van Macomb and Ron Warner, Lattice Semiconductor

 

Introduction

FPGAs have played an integral role in the development and deployment of wireless infrastructure over the past twenty-five years.  Insiders know that the wireless equipment market spans the gap between high volume FPGA production runs and low volume ASIC production runs.  Base stations have been the historical demarcation point as device volumes for base station upgrades and full scale deployments can run in the tens of thousands to hundreds of thousands.

 

 

 

 

Figure 1- Femtocell Topology

 

With the advent of low cost femtocells and their heralded potential for millions of units, the outside observer might conclude that FPGAs have finally run their course in this application space.  This article will review a femtocell architecture that will show how innovative new FPGA architectures are still an integral part of the femtocell revolution.

 

Femtocell Architectures

Femtocells are small form factor base stations designed to fit into a home and support a single family or a handful of subscribers.  A variety of deployment scenarios, encompassing rural settings as well as suburban and city dwellings are envisioned for these mini-base stations, which are also known as Access Point Base Stations. Shown in figure 1 is a simplified view of the overall topology of how the network could be configured. Femtocells are poised to become the ultimate delivery vehicle for wireless infrastructure expansion because:

 

  • They will support existing 3G handsets
  • Wireless network capacity is expanded on a local as-needed basis
  • CAPEX costs are shifted to the consumer
  • The backhaul bottleneck is bypassed as consumers link their femtocells to their wired (cable or fiber) home connection.

 

Using this simplified definition, it is clear that a femtocell base station must support the same high level, functional features as traditional base stations. In addition, the home is viewed as the ideal location for delivering value added features such as true high quality voice, faster data, music download center, home intercom, etc.  The home-located base station also holds tremendous potential for advertisers to deliver highly targeted messages and campaigns right to the subscriber’s home.  All of these factors underscore the need for flexibility in architecting femtocells, especially in this initial deployment phase. 

 

 

Figure 2 - Simplified Femtocell Block Diagram

 

Femtocell Simplifications

The home environment does simplify some of the requirements of a femtocell, which in turn opens several options at the device level for implementing these features.  First, a femtocell is intended only to support a handful of users, which greatly reduces the overall system processing requirements.  Second, unlike traditional base stations that support end-users speeding along in cars, femtocells need only support mobility as it applies to people walking about their homes.  This greatly simplifies the search algorithms needed to find and support them.  These two major differences make it possible to implement a femtocell base station using just a handful of chips (Figure 2). 

 

Femtocells - A Closer Look

A more detailed look at this exciting new deployment scheme quickly uncovers some of the complexity associated with it and begins to reveal why FPGAs are still integral to its success.  First, what are the various backhaul technologies that consumers will plug into (FTTx, Ethernet, ATM, DSL, etc.), and how does that impact the femtocell design?  Second, what are the air interface standards that need to be supported?  Although most of the discussion here is focused on WCDMA/HSPA and CDMA/EV-DO, the massive footprint of deployed GSM technology requires a look at supporting this standard as well.  And if WIMAX and WiFi femtocell designs gain traction, should these also be supported?  At the same time, some of the complexities associated with having a base station in the home, such as security, access control, interference with the macro cell, handouts and handins have yet to be resolved.  All of these variables again underscore the need for flexibility in architecting femtocells. 

 

Femtocell Cost Pressures

With the anticipation of a femtocell in every home comes the inevitable pressure to minimize cost.  Price targets for a complete femtocell in the range of $100 to $200 are being discussed.  These price points are well below the cost of today’s full featured, flagship FPGAs. 

 

Fortunately, this relatively new base station architecture is emerging at a time when low cost FPGA architectures have rapidly grown in popularity, to the point that they now represent approximately 25% of the overall market.  FPGA vendors have developed low cost FGPA fabrics with embedded features such as DSP blocks, embedded memory and even high-speed SERDES that support the performance requirements of wireless Baseband processing at a fraction of the cost of full featured, high-end FPGAs.   

 

Traditional DSP/FPGA Processing

FPGAs and DSPs have been co-processing partners in wireless applications for many years.  With the advent of low cost, feature rich FPGAs and processors specifically developed for wireless applications, this symbiotic relationship remains viable for anticipated high volume femtocell applications.  These scaled down processors offer the functionality needed to support the reduced requirements of a smaller base station and are significantly less expensive than their highly integrated counterparts.  A summary of the partitioning options between processors and FPGAs is shown below. 

 

 

 

As the traditional wireless infrastructure was built, many of the functions shown above were moved from FPGAs and Communications Processors to ASICs.  This process takes many years, and initial deployments without ASICs were quite common.  It is anticipated that the early days of femtocell deployments will follow the same historical path.  Consequently, a number of the ASIC functions shown above initially will be implemented in either low cost FPGAs or specialized Communications Processors.  As an example, base band chip rate processing can be partitioned such that a Rake Receiver, RACH detector, spreading, scrambling and channel weighting/summing functions are all offloaded from the processor to a hardware implementation.  Additionally, symbol rate processing functions such as a turbo decoding, modulation and symbol mapping also are viable candidates for hardware acceleration.  FPGA devices such as those in the LatticeECP2M family make hardware-based solutions such as this attainable in a single, highly integrated, low cost device.  This is made possible by providing traditional, high-end, feature rich functionality such as embedded DSPs, memory blocks and high-speed serial interfaces, at price points that allow system designers to keep pace with the aggressive pricing in the femtocell market.

 

Baseband Implementation Example: Rake Receivers

Rake Receivers are a key element in optimizing the received signal quality in wireless communications, especially as they relate to W-CDMA/UMTS. In an outdoor environment, where multi-path interference and fading must be dealt with, more fingers may be needed in the RAKE to ensure the quality of the call at the cost of more complex Rx circuitry. In contrast, for a femtocell the less hostile, fixed mobility nature of the home environment means these requirements can be simplified. In turn, this opens several options at the device level regarding the implementation of these features. One of those architectural options to be considered is the reduction of the number of fingers needed in the Rake Receiver, which simplifies the design and more importantly allows for a lower cost implementation. Since there is active discussion regarding the number of fingers required in a given femtocell environment, this further underscores the value of a flexible, low cost, hardware-based implementation. 

 

Maximum Ratio Combining (MRC) is a common rake receiver implementation that gathers the signal energy coming from different paths. This information is used to decide the number of fingers that should be allocated for a specific user and to calculate the initial delays or finger offsets.  Each finger is implemented as a small Correlator that is weighted, multiplied by the finger output and then combined to give MRC output.  This MRC function and its implementation in an FPGA are illustrated in Figure 3.

 

 

 

 

 

 

 

Cn(t) = C(t+delay(n)) delayed version of orthogonal code C(t)

Pn – Path(n) power factor calculated by Processor

 

 

 

Figure 3 - RAKE Receiver Muti-Path Combiner

 

 

 

The Advantage of Programmability

 

The relative advantages of ASICs, stand-alone ASSPs and FPGAs are well understood by the major wireless infrastructure providers.  For applications involving emerging specifications, or where custom logic is needed, programmability is a key advantage and necessity for the designer.  Programmability gives system designers the ability to design a single hardware platform that can incorporate vendor-specific logic and also be used to provide multi-regional solutions. 

 

As small form factor base stations that support mainstream wireless handsets, femtocells clearly will need to support the same path from 3G and its releases (HSDPA/Adaptive Antennas/MUD/PA linearization) to 4G.  In addition, femtocells will add unique value-added features that take advantage of the home location.  Many of these features will be specific to certain regions of the world and are still being defined. 

 

As CPE based wireline and wireless networks converge into the contiguous femtocell, it is also clear that Ethernet will have a key role to play in the femtocell backhaul.  As such, a key consideration for FPGA selection will be the availability of on-chip embedded high speed Ethernet interfaces.

 

Most importantly, operators have stated that the femtocells must meet certain cost targets to be successful.  Low cost FPGAs are now available that provide the necessary SERDES, programmable logic and DSP functionality to support femtocell implementations at price points that were previously unachievable with high end FPGAs or ASSP/FPGA combinations.  These low cost FPGAs combine programmable logic with embedded features such as DSP blocks, embedded memory and SERDES.  In conjunction with specialized processors, these new low cost devices are an attractive solution for femtocell implementations.   

 

Conclusion

 

Wireless equipment vendors have relied on FPGAs to implement multiple functions as technology has evolved.  Femtocells represent another step in this exciting evolution, and are another example of a wireless innovation that will take advantage of the flexibility provided by today’s low cost FPGA architectures, especially during the initial deployment phase.  These advantages include rapid time to market, the ability to accommodate changes in the specification without modifying hardware, the flexibility to implement differentiating features and integrating multiple functionality onto one chip:  all at cost points that still support high volume, low cost deployment.