Adaptive Clock Recovery for Metro Ethernet Networks

by Tao Lang, Wintegra

Introduction

Carriers are building metro Ethernet networks to provide high-speed data services in a standard form, to be compatible with today's enterprise backbones. However, the new networks must also continue to support legacy services such as TDM, Frame Relay, and ATM. When transporting TDM traffic such as T1/E1 circuits over Ethernet, synchronization becomes a major challenge. In many situations, adaptive clock recovery is the only means of providing a viable solution, and this article describes how it can be used to provide a seamless transition to the new services.

In order to transport T1/E1 circuits over Ethernet, the network must encapsulate the T1/E1 bits into Ethernet frames. The Ethernet frames are then launched at a rate determined by the T1/E1 frequency. The term ‘adaptive clock recovery' refers to a set of techniques for replicating the original T1/E1 frequency at the remote end of the network after the Ethernet frames have been received.

Each Ethernet frame will experience different delays when traversing the network, resulting in irregular arrival times. A key task of the adaptive clock recovery algorithm is to filter out such irregularities, and recover a stable and accurate clock frequency. In order to be able to achieve this, one must first be able to characterize the delays.

Network delay

The network delay of an Ethernet frame is affected by several parameters, including the routing path, loading, and queuing mechanism of each switch or router it traverses. Moreover, QoS-related mechanisms such as traffic policing and shaping often make the frame delay more unpredictable. Network impairments such as congestion, packet loss, and routing change will also adversely affect the adaptive clock recovery performance.

A robust clock recovery solution must take all these effects into account, and be able to deliver acceptable performance in typical network environments. The ITU-T G.8261-draft standard contains guidelines on what is considered to be acceptable and typical.

Today, most GSM/UMTS basestations are connected to mobile central offices through physical T1/E1 lines. Adaptive clock recovery enables wireless operators to transport the T1/E1 links over an Ethernet or IP network while still keeping basestations synchronous, a popular approach that reduces backhaul leasing cost significantly. This is made possible because Ethernet services are significantly cheaper than T1/E1 lines. Many hardware manufacturers are offering chips or cards to simplify such connections. For example, Wintegra offers a complete solution for a network interface card in 2G/3G basestations: its access network processor can bridge any type of network interface, such as IP, ATM, or TDM, to the basestation backplane. The addition of an adaptive clock recovery solution enables the synchronization of basestations when T1/E1 backhaul is carried over packet switched networks, eliminating the need for costly GPS receivers or expensive highly stable oscillators.

Figure 1: WinPath-based solutions for  CESoPSN and SAToP

A proprietary adaptive clock recovery algorithm, running on its packet processor in data path software, enables the Wintegra solution to meet the G.823 and G.824 jitter and wander masks in traffic conditions as defined by the Metro Ethernet Forum and G.8261-draft, as well as meeting the more stringent requirements of 3G applications. The result is a complete solution for multi-service access that supports the termination of multiple protocols – including ATM UNI, IMA, PPP, ML-PPP, FR, MFR, ATM CES and PWE3 (pseudo wire emulation edge-to-edge) – which can be used at the same time over different T1/E1 interfaces. The newly added PWE3 protocols support the transport of different formats of data (TDM, ATM, HDLC) over packet networks.

As for the Wintegra TDM PWE3 solution, two densities are available: the low-density 8/16 T1/E1 (256/512 DS0s channels) using only external framers, and the high-density channelized OC-12 (336 T1/252 E1) solution using an external FPGA with a proprietary IP core and a framer/mapper. Once the protocols (in most cases using draft-ietf-pwe3-satop or draft-ietf-pwe3-cesopsn) are terminated, the data can be inter-worked to a cell or packet backplane or uplink, either by using switching, bridging or MPLS routing. Wintegra's adaptive clock recovery solution covers for both densities. Clocks can be recovered either at the low-density CPE end driving discrete T1/E1 lines, or at the high-density aggregation point driving T1/E1 tributaries into channelized OC-3/OC-12 pipe.

Conclusion

Carriers are trying to converge all new and legacy services on to a single platform, a packet switched access network such as metro Ethernet. This will allow them to reduce both capital and operating costs and simplify their networks. However, when transporting TDM circuits such as T1/E1 over metro Ethernet, adaptive clock recovery may be necessary to maintain synchronization. The integrated hardware and software described here can help to provide a complete PWE3  implementation with advanced adaptive clock recovery algorithm and performance.

About the Author

Tao Lang is the product manager for Wintegra's Multiple Service Access product line, which supports protocols including PWE3, MLPPP, MFR, IMA and ATM. Prior to joining Wintegra Tao worked as senior applications engineer at Zarlink Semiconductor (formerly Mitel Semiconductor) for over 10 years. He has a MEng degree from the National University of Singapore.