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Flexible Digital Front-End Design for TD-SCDMA Tim James, Sam Chalmers and David Kenyon – Multiple Access Communications Ltd Introduction The advent of software-defined radio (SDR) heralds the ability for the designers of wireless base station (BS) equipment to be able to support a wide variety of equipment configurations and radio frequency (RF) standards using ‘generic' hardware platforms. The realisation of such systems has many potential benefits; development costs can be spread across multiple product lines; new and customised product variations can to be brought to market more rapidly; and existing products can be upgraded in response to evolving RF standards. Using the latest FPGA, DSP and converter technology, hardware designers can now develop flexible platforms capable of supporting a wide range of product configurations. At first sight this appears to greatly reduce the design task, but closer inspection reveals that there has simply been a shift in the balance between hardware and firmware; the reduction in hardware design has been replaced by a greater need for firmware. Every product variant will require a different firmware build, with each incurring significant development effort. Base stations for cellular radio networks come in a variety of shapes and sizes. At one end of the scale there are single carrier, single antenna devices for use indoors or in areas of low subscriber density. At the other end of the scale there are BSs that deploy perhaps six carriers per sector and use adaptive antennas, with up to eight elements, to provide enhanced performance. What they all have in common, however, is the requirement to receive a RF signal from an antenna, convert it to baseband and separate the wanted signal from others picked up by the antenna. The transmit path essentially performs the same operations but in reverse. When implemented in the digital domain, the resulting subsystem is typically referred to as a digital front-end (DFE). An example showing the function of a DFE in a typical system is shown in Figure 1. In general terms the underlying signal processing tasks primarily involve filtering and mixing, with the same sequence of operations performed on each antenna/carrier pair regardless of how the BS is configured. The modular and repetitious nature of multi-channel/multi-antenna DFEs lends itself to the use of software tools that allow the development of new firmware designs to be accelerated. Moreover, in order to minimise the time taken to assemble new design variants, the design engineer should be able to concentrate on the high-level system architecture and not have to worry about the low-level design and implementation of the core signal path building blocks. Obviously, the detailed design of the filters and mixers cannot be overlooked. However, it is possible to carry out this task once and then to encapsulate the results so that the designer can construct other designs at the system level, freed from the task of re-designing the detailed signal processing functions for every product variant. In this article, we'll show how a library of pre-verified intellectual property (IP) building blocks developed for use with Xilinx® System Generator for DSP can be used to rapidly assemble a range of DFEs for different BS configurations with confidence that all conformance criteria will be met. The realization of this goal has the potential to deliver huge savings in design time when measured over the lifetime of a cellular BS product.
Figure 1: Generalised DFE system.
Coping with Complexity The function of the BS DFE shown in Figure 1 can be split in two halves. Up-conversion, ie, the downlink transmit path, is handled by the digital up-converter (DUC). The function of the DUC is shown in more detail in Figure 2. Down-conversion, ie, the uplink receive path, on the other hand is handled by the digital down-converter (DDC), which is shown in Figure 3. These figures show the design of a DFE developed for use with the time division-synchronous code division multiple access (TD-SCDMA) system, part of the 3G cellular radio standard. In addition to performing the frequency translation and pulse-shaping operations, the DFE shown supports the implementation of burst gain profiling on the downlink and programmable channel gain and signal path delay on the uplink. Although this article focuses on the TD-SCDMA DFE, we note that DFEs for other radio systems would have a similar function and structure. At the system-level, as typified by Figure 1, there is an obvious, regular structure to the design. It is at this level that a BS designer would ideally wish to work. At the lower levels complexity increases significantly. Moreover, as readers familiar with designing DSP systems will be aware, each of the blocks shown in Figure 2 and Figure 3 can be implemented in a variety of ways. To make optimum use of the FPGA resources available, the low-level blocks will typically employ resource sharing; using the highest possible clock frequency (the TD-SCDMA DFE library discussed in this article is optimised for use with a 307.2 MHz system clock) to make the most efficient use of key FPGA resources such as DSP48s and block RAMs (BRAMs). Such techniques require careful design to ensure that the blocks will meet the required timing constraints when the FPGA is built. Furthermore, there is considerable complexity to be found in the scheduling of the data paths to ensure that the desired signal processing functions are implemented correctly. It is this complexity that we seek to hide once the low-level blocks have been designed and their operation verified. For any given DFE configuration it is easy to see how the design details can be hidden by the design hierarchy and System Generator inherently provides the mechanisms to do this. However, this is not sufficient. What we require is a way of enabling a BS designer to re-configure the DFE without the need to delve into the details of working with the low-level blocks shown in Figure 2 and Figure 3. One approach might be for the library designer to pre-configure top-level blocks corresponding to each of the expected configurations. But this simply transfers the complexity from the BS designer to the library designer and does not provide true flexibility as the supported configurations will be fixed when the library is designed. The solution that we have adopted in the design of the TD-SCDMA library is to build top-level blocks that each support one antenna and up to six carriers. When less than six carriers are required the unused channels can be simply terminated and internal mechanisms will ensure that the unused logic is removed during the build process. This approach delivers ease of use whilst ensuring that the final design makes efficient use of FPGA resources.
Figure 2: Six-channel DUC signal path.
Figure 3: Six-channel DDC signal path.
Creating Designs using the DFE Library The use of the TD-SCDMA DFE library is simplified by the fact that most of the DFE functionality is implemented in just two blocks (a six-channel DUC and a six-channel DDC) with additional blocks provided to allow different IF mixing options to be selected and to simplify the task of adding data interfaces to the design. An example showing the core of a six-channel DUC constructed using the DFE library blocks is shown in Figure 4. Most of the signal processing is performed within the six-channel ‘TD-SCDMA DUC (6 Channels)' block. The ‘Local Oscillator' and ‘DUC Mixer' library blocks are added to allow the composite output of the DUC to be translated from zero to a more practical intermediate frequency (IF). This subsystem generates the output for a single antenna. Multi-element antenna systems can be supported simply by replicating this once for each element. So, supporting an arbitrary number of antennas is relatively straightforward. What about designs that require fewer than six carriers? To use a ‘full' six-carrier design in such circumstances, although a perfectly valid solution, would lead to an unnecessarily large FPGA design. In the worst case, this might prevent the use of a smaller device and hence greatly increase the cost of the solution. Solutions that require the user to manually remove any unnecessary logic or that involve the implementation and supply of a complete set of pre-defined variants clearly defeat the purpose of the library, which is to distance the user from needing to understand the intricacies of the design. Instead, as mentioned in the previous section, the DFE library has been implemented with some additional features that help the downstream design tools optimise away unused logic at build time. Thus, the user simply terminates unused inputs using a library block provided for the purpose. An example of a three-channel DUC design is shown in Figure 5. Here, Channels 3 to 6 have been tied off using the ‘Unused BB Input' block and the control inputs for these channels, which are no longer required, are tied to constant values. Now, although this design is constructed using the six-channel DUC subsystem, all the logic, BRAM and DSP48s dedicated to the unused channels will be removed at build time. There is a similar story for the DDC. An example six-channel, single antenna design is shown in Figure 6, with a three-channel variant shown in Figure 7. With the DDC, unused channels are optimised away simply by terminating the unused outputs (using standard ‘Terminator' Simulink blocks) and tying unused control ports tied to constant values. As with the DUC, multiple antennas can be supported simply by duplicating the single-antenna design.
Figure 4: Example 6-channel DUC for a single antenna.
Figure 5: Example 3-channel DUC for a single antenna.
Figure 6: Example 6-channel DDC for a single antenna.
Figure 7: Example 3-channel DDC for a single antenna.
Performance It is important that the flexibility desired is not achieved at the expense of reduced RF performance. The DUC and DDC solutions implemented by the TD-SCDMA DFE library have been designed to comfortably exceed all the relevant requirements of the TD-SCDMA radio technology. In most cases the margin is many tens of dBs to allow as much headroom as possible for degradation by other, eg, analogue, stages of the signal path. The ability to effectively remove logic, DSP48s and BRAM associated with unused channels is an important requirement of any flexible DFE solution. As an example, when ‘built' a three-channel DUC created using blocks from the TD-SCDMA DFE library discussed in this article requires approximately 70% of the resources required for the ‘full' six-channel block. A three-channel DDC uses around 60% of the resources required by all six channels. We note that in the resource reduction does not scale directly with the reduction in the number of channels and cannot equal 50% because some parts of the signal path are common regardless of the number of channels used (as shown in Figure 2 and Figure 3). Conclusions The flexibility of FPGAs solves the hardware designer's dilemma of how to provide a platform to cater for a range of product variants, but in doing so transfers the problem to the FPGA firmware designer. In the environment of a cellular base station the range of product variants share many common elements and with careful design this can be exploited to simplify the firmware designer's task. Using a TD-SCDMA DFE library developed for use with System Generator as an example, we have shown how a library of pre-verified IP may be developed in a way that clearly separates the system-level design from that of the detailed DSP tasks. This combination of system-level design tools and IP can greatly reduce the design time, hiding the detailed complexity of low-level implementation thereby allowing designers to concentrate on the product architecture. Furthermore, providing a clear separation between the system-level and DSP-level designs facilitates the migration of designs to new FPGA devices, engendering similar advantages that object-oriented programming brings to software design. The DFE library for TD-SCDMA was developed to target the Virtex™-4 family of FPGAs on behalf of Xilinx by Multiple Access Communications Limited, a consultancy company based in Southampton, UK. The library is provided with example designs for hardware co-simulation and a working full-speed demonstration design targeted at the Virtex-4 variant of the XtremeDSP development platform. The library has been extensively verified and proved to exceed the requirements of the relevant 3GPP specifications. Sam Chalmers is a Principal Engineer with Multiple Access Communications Ltd (MAC Ltd). Sponsored as an undergraduate by the Defence Evaluation & Research Agency (DERA), he graduated from Southampton University in 1998 before joining MAC Ltd. Upon joining the company, Mr Chalmers was involved in the development of MAC Ltd's range of radio network planning tools and propagation algorithms. Since 2000 Mr Chalmers has been predominantly involved in the design, implementation and testing of embedded DSP systems for a number of internal and external projects. These projects include the development of a receiver for drive testing TETRA networks, and a project to build and evaluate a system for electromagnetic capability conformance testing using time-domain measurement techniques. Mr Chalmers is a Member of the Institution of Engineering and Technology and a Chartered Engineer. David Kenyon is the Managing Director of Multiple Access Communications Ltd (MAC Ltd). After graduating in 1984, he joined Plessey Research Roke Manor, before moving to Shaye Communications Ltd in 1986. Mr Kenyon joined MAC Ltd as Technical Director in February 1992 before being promoted to the role of Managing Director in June 2004. Since joining MAC Ltd, Mr Kenyon has been involved in a wide variety of consultancy and product design projects and has been responsible for directing all product development related business, with an emphasis on digital signal processing and FPGA design. Mr Kenyon also maintains an active engineering role and frequently acts as a systems consultant to projects. Mr Kenyon is a Member of the Institution of Engineering and Technology and a Chartered Engineer. |
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