Integrated Clock Generators Enable Smaller Basestation Form Factors and Help Reduce Cost

By Matthias Feulner, Texas Instruments,

Business Development Manager Wireless Infrastructure

Oscillators & Synthesizers

In a typical system requiring high-speed timing signals – whether Telecom, Datacom, Medical or similar – usually a system timing reference is derived from either a GPS signal or from a network timing signal in a ‘master timing unit.’ This synchronizes the timing reference with an extremely stable, precise and low-noise oscillator, usually a temperature controlled crystal oscillator (TCXO) or oven-controlled crystal oscillator (OCXO). Then it is distributed at modest frequencies (typically below 10 MHz) to subsystems that need to operate synchronously at a fraction or a multiple of the reference clock rate. Often this involves subsystem functions that require a high quality clock source with high precision, little drift over time, and low phase noise / jitter. Examples are clocking data converters or serial link interfaces.

Figure 1: Clock generation and distribution in a typical (wireless base station) system

In this clock distribution concept (see Figure 1), phase-locked loops (PLLs) and voltage-controlled oscillators (VCXO) play an important role. The VCXOs provide low phase noise clock signals when needed in subsystems. The PLLs are used for synchronizing the system reference clock, which may have picked up various dirt effects during distribution, with the local VCXO.

Figure 2: Integer-N PLL block diagram

Figure 2 shows the integer-N PLL principle. A reference clock with frequency fref and a local oscillator clock from a VCXO with frequency fVCXO enter the PLL. In order to lock the reference and the local oscillator to each other, both are compared with respect to phase and frequency in the phase frequency detector (PFD). Typically the reference clock frequency may be different from the local oscillator. Hence, in order for them to match the PFD with a common comparison frequency fPFD, reference divider R and feedback divider N may be set accordingly. This allows the two clocks to lock with each other at almost arbitrary integer and fractional ratios, depending on the depth (range) of the dividers. The VCXO can be tuned within a certain frequency range applying an analog control voltage Vctrl . This voltage is generated by a charge pump that produces current pulses that are then low-pass filtered by the loop filter and turned into the control voltage. Depending on the mismatch between fref and fVCXO, the charge pump will generate positive or negative current pulses, increasing or decreasing the control voltage until both frequencies are equal. This is when the PLL is said to be “locked,” both in terms of frequency and phase.

Phase noise properties of the of the PLL output are influenced by various factors. The most important are:

· Phase noise of the reference

· Phase noise of the VCXO, typically exhibiting very good phase noise close-in (close to the fundamental frequency)

· Noise contribution of the PLL components, a potential limiting factor for the phase-noise floor far-off (at large offsets from the fundamental frequency)

· Divider settings, a division of the clock frequency by a factor of two, reducing phase noise by 6 dB.

· Loop filter design, the choice of the loop filter bandwidth allowing to optimize phase noise contributions of the reference (dominating output noise inside the loop filter bandwidth) and the local oscillator (dominating outside the loop bandwidth)

In the past, integrated solutions suffered from low finesse ‘Q.’ Therefore, VCXOs were the only choice for superior phase noise performance. Today, with improved semiconductor process technology and design techniques, considerable performance improvements are possible when implementing entire PLLs including the VCO on-chip.

Integration Approach

Integration may help both with the implementation of VCXOs (9x14mm), as well as for complete PLL synthesizer modules (approximately 22x17mm). These are designed and manufactured by companies specializing in oscillator technology. Subsequently they are delivered, often according to customer specifications, as subsystems for use in various applications like wireless base stations, SONET/SDH wireline networking, routing and switching, storage are networking, military and others. An integrated clock generator that can be used for both oscillator and PLL synthesizer applications is the CDCE421 from Texas Instruments.

Figure 3: CDCE421 Integrated clock synthesizer

In this approach, a high-frequency and low-noise voltage-controlled oscillator (VCO), PLL, loop filter, differential output buffer stages for LVDS and LVPECL, as well as an EEPROM and a 1-wire programming interface, are integrated on the same chip. The output frequency of the integrated device results from the following equation:

In order to maintain high-Q, the tuning range of the VCO is limited. Hence, two separate VCOs running at up to >2 GHz are used alternately for continuous frequency coverage between 11.8 MHz and 1175 MHz. By dividing the output frequency down from the fundamental VCO frequency, an improvement in phase noise of 6dB can be achieved for each division by two as mentioned earlier.

Application Potential

Small Form-Factors, High Frequency XOs & Configurability

Oscillator module applications provided with a low-frequency crystal reference may benefit from using the CDCE421 in ‘oscillator mode’ in multiple ways:

·Small Form Factor: Shrinking the oscillator module to the minimum possible size is determined by the crystal, as well as the attached circuitry for implementing the Gain stage, output buffer and trimming of the frequency, with concepts of double sided PCBs already in use today. Complex system may use multiple oscillators. Thus, the need for smaller form factors is driving miniaturization. The ability to implement 5x7mm modules with a die size of only 1.7x2 mm, is a major differentiator for the CDCE421.

Figure 4: 5x7mm oscillator module implementation using CDCE421

·Lower cost high-frequency XOs (Crystal oscillators): For high-frequency applications requiring 500 MHz clock frequency and beyond, a dominating factor that affects cost is the availability of high-quality crystals. Examples include the 491.52 MHz or 983.04 MHz clock in UMTS base stations, or the 622.08 MHz in SONET/SDH networking equipment. While these frequencies often are generated using a third overtone approach, filtering out one of the higher-order harmonics of the crystal (the raw crystal material) remains costly. Equipped with a low-frequency crystal or VCXO reference, the CDCE421 can help implement high-frequency XOs at a significantly reduced cost.

·Configurable Oscillators: XOs often are built according to customer specification. Aiming for shortest turn-around time and optimized inventory management favors the use of a flexible platform. The single-wire programming interface of the CDCE421 allows the integrated clock generator to be configured, even after the oscillator module has been already assembled. This significantly simplifies the production flow with the possibility to pre-assemble most of the module beforehand, and adding the frequency-determining low frequency crystal as needed. In combination with a built-in EEPROM, the configuration step can be completed simply during final testing of the module. With data now stored on the module, there is no need to re-configure again during a new system start-up.

High-Frequency Clock Synthesis for Data Converters

Wide-band multi-carrier transmitters in wireless base stations employing digital power amplifier pre-distortion are driving the need for high sample rate digital analog converters (DACs). Supported signal bandwidths are already reaching as much as 20MHz. The power amplifier pre-distortion feature adds a factor of five times. Non-linear products usually need to be corrected up to the fifth order. With an aggregate transmit bandwidth of 100 MHz, sampling rates today are reaching 491.52 MSPS. The trend is going towards twice that amount. On the other hand, clocking requirements for the analog-to-digital converters (ADCs) in the receiver usually are much lower in frequency. An example is the order of 61.44 MSPS, which is much more stringent in terms of (close-in) phase noise.

Figure 5: Wireless Infrastructure transceiver with traditional clocking scheme

This in turn is asking for very costly VCXOs to deliver the DAC reference clock. To keep costs down, an attractive alternative is to use a much lower frequency VCXO to deliver the very low-jitter clock for the ADC. Then use the CDCE421 in ‘synthesizer mode’ to generate the higher clock frequency for the DAC.

Figure 6: Wireless Intrastructure with CDCE421 based clocking scheme

Performance Demonstrated

In Figure 7, the performance of the CDCE421 is investigated in a configuration generating a 491.52 MHz clock commonly used for driving DACs in WCDMA wireless base stations from a 30.72 MHz VCXO reference.

Figure 7: Clock generator performance evaluation setup

The performance of the clock generator is verified in two ways. First, we check for clock spurious components in the DAC output spectrum and find these to be more than 60dB below the signal.

Figure 8: DAC5687 output spectrum with clock spurs

Then we determine the error vector magnitude (EVM) of the DAC output. This is a measure for deviations of the data pattern from the ideal position in a modulation constellation diagram. The goal is to stay at less than one percent.

Figure 9: DAC output signal analysis

Summary

New integrated clock generators are supporting current trends towards miniaturization, flexible configurations, and cost reductions in VCXOs, as well as the needs for optimized system clocking in complex applications like data converter clocking.

References:

[1] Fractional- / Integer-N PLL Basics: http://www.ti.com/litv/pdf/swra029

[2] CDCE421 Data Sheet: http://focus.ti.com/docs/prod/folders/print/cdce421.html