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By Louis Belanger, CTO – Lyrtech
Introduction
In the actual context of today’s maturing wireless infrastructure industry, developers and manufacturers need to streamline their capacity to both increase functionalities with their final products and beat time-to-market and cost pressure constraints. The arrival of initiatives such as OBSAI and CPRI and their continuous establishment as open architectures for standardizing the interfaces between the radio (RF), base band processing (BB), transport and control BTS building blocks are setting the pace for the development of optimized, open and more connective hardware to allow developers cut on costs and beat the clock on the race to the market place.
In this evolving context, the developer is faced with the challenge of supporting these emerging and somewhat competing standards while maintaining support to a number of in-house and/or legacy approaches. Specifically for the high-speed RF-BB interconnection, the need for a high-performance reprogrammable part such as an FPGA arises.
An FPGA-based OBSAI/CPRI development platform is then a definite plus for the BTS developer. However, to cover the needs of the entire market, it needs to provide support for both OBSAI and CPRI standards as well as all high-speed interconnect approaches, both electrical and optical. The Lyrtech OBSAI/CPRI Virtex-4 Development Platform, based on Virtex-4 FPGAs and jointly developed with Xilinx, aims at providing the BTS developer such flexibility in terms of high-speed RF-BB interfaces for both OBSAI and CPRI specifications.
The RF-BaseBand interconnection
The RF-BB physical interconnect is basically a high-speed “single wire” connection on which serialized based-band IF data streams are transmitted. Either differential LVDS pairs or optical fiber can be used. Data rates vary from 614 Mbps to the 3 Gbps range. Multiple RF modules can be connected: for example, the RF-BB specific RP3 section of the OBSAI specification (see figure 1) allows for a maximum of nine pairs either arranged in a mesh or a centralized combiner and distributor (C/D) topology.
Figure 1 OBSAI and CPRI base station modules
A Suitable Solution
A development platform with the following features becomes a one stop solution for the BTS developer.
Powerful FPGAs
The power and capacity of the FPGAs used on the development board provide developers the necessary programmability to much faster and readily test and prototype their designs. The Virtex-4 family FPGAs feature Power PC processor blocks, RocketIO™ Multi-Gigabit Transceivers, Ethernet MAC blocks and XtremeDSP™ Slices offering great processing power. Reference designs and IPs available from Xilinx complement a large array of either OBSAI or CPRI applications that run on the Lyrtech OBSAI/CPRI Virtex-4 Development Platform. However, details about such reference designs and IPs are not the subject of the current document.
Various Clock Sources for Multirate Data Flow
Data can flow in a multitude of rates thanks to PLL circuitry that uses a dual-frequency VCXO that allows stable clocking for both OBSAI and CPRI designs. The PLL will use different clock references such as the on-board OBSAI or CPRI clock oscillators, any other external clock references (through the SMA interface) or high-speed interface recovered clocks (SERDES, MGTs). Also, other on-board clock oscillators should be used as references for SRIO and Ethernet data flow. Such clock availability represents a great flexibility to accommodate most of the OBSAI/CPRI applications.
Highly Connective and Versatile Platform
The large array of interfaces and interconnections populating the platform should offer developers the flexibility to test data and evaluate performance using different standards and communication speed rates. Therefore, implementing and testing their designs with the possibility to interface with numerous external devices and at higher speeds than ever before becomes not only an appealing option but a must-have feature.
Lyrtech OBSAI/CPRI Virtex-4 Development Platform
The Lyrtech OBSAI/CPRI Virtex-4 Development Platform consists of two clusters containing a Virtex-4 FPGA (one LX60 and one FX60), an external SERDES, Gigabit Ethernet connectors, and DDR2 memory. Therefore, the platform can send and receive data at rates ranging from 614.4 Mbps to 3072 Mbps via the SMA interface, connected to the LX60 Virtex-4 FPGA through an external SERDES and the on-board SFP, the HSSDC2 interfaces connected to the RocketIO™ Multi-Gigabit Transceivers in the FX60 Virtex04 FPGA. Also the data can be sent and received via a SRIO interface at rates ranging from 1250 Mbps to 3125 Mbps directly connected to the RocketIO™ Multi-Gigabit Transceivers in the FX60 Virtex-4 FPGA.
For inter-FPGA communication, a RapidCHANNEL Bus allows data exchange between the FX60 and the LX60 Virtex-4 FPGAs at up to 8 Gbps, Full-Duplex.
Figure 2: Lyrtech OBSAI/CPRI Virtex-4 Development Platform and connectivity diagram
To facilitate connectivity with other telecommunications system components, conversion modules from Xilinx are available to convert SMA interface inputs into SFP or HSSDC2 data. Test and measurement equipment can be easily connected thanks to the multiple Ethernet interfaces available, allowing for a probe point in the communication path from which the user can either add or retrieve data. Therefore, the Ethernet interfaces can be used for monitoring purpose to detect special events/data just like a “sniffer” or protocol analyzer.
The platform also has expansion capability and provision for add-on modules from Lyrtech’s catalog of communication oriented I/O and RF boards, allowing it to be used as either a base station RF module or a base station baseband processing module. OBSAI/CPRI Bridging
The OBSAI/CPRI Virtex-4 Development Platform can serve as a peripheral bridging ‘swiss knife’ device for the different high speed interfaces of a modular BTS.
In a typical development scenario, the developer will connect a legacy or new equipment under-development through the OBSAI/CPRI Virtex-4 Development Platform acting as a bridge to different OBSAI/CPRI sources and/or sinks. Test equipment can also be connected to the platform, allowing monitoring and analysis of the different data streams. Once the testing has been completed, the developer can recover all FPGA IPs and design code and use it to develop a final product.
Another scenario is to use the platform as a customisable OBSAI/CPRI sink or source, where different OBSAI/CPRI applications can be programmed for test purposes.
Figure 3 Typical connectivity configuration in an OBSAI/CPRI development context
As shown in the picture below, the data flow is bidirectional; it travels across the OBSAI/CPRI Virtex-4 Development Platform using the following path: RX SMA connectors → SERDES → XCV4LX60 → 8 Gbps Inter FPGA bus → XCV4FX60 → SFP, HSSDC2 or SRIO. The same path is used in the other direction: SFP, HSSDC2 or SRIO → XCV4FX60 → 8 Gbps Inter FPGA bus → XCV4LX60 → SERDES → TX SMA Connectors.
Figure 4: Bidirectional data flow
A Future Well Thought Of
Based on the powerful capabilities of Xilinx Virtex-4 FPGAs and combined with fully integrated OBSAI and CPRI cores, the platform allows the designer to concentrate on its task to develop advanced capabilities and product differentiation features in a BTS modularisation trend, while maintaining legacy capabilities. Enhancing modular BTS testing is also a key outcome of such a platform. Base station designers and manufacturers can count on a piece of hardware that will easily evolve along with the upcoming needs of the market and the new trends from the industry.
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