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Downconvert 64 channels using just one FPGA
By Simon Underhay, RF Engines
Summary
RF Engines' ChannelCore64 allows designers to replace up to 16 specialist DDC ASIC devices with a single IP core for FPGA, significantly reducing board area, lowering power consumption, and increasing flexibility. The new approach represents a major cost saving over traditional methods, with savings becoming more significant as the number of channels increases. It also reduces the power consumption while providing total flexibility and ease of design. ChannelCore64 is targeted at applications such as wireless base stations, satellite ground stations, and other multi-channel radio receivers. In many of these systems, there is a need for extracting numerous channels (signals) of different bandwidths, from a very wideband signal, and then matching these channels to the following part of the overall system to simplify its design.
ChannelCore64
Almost all radio receivers need to extract one or more relatively narrow channels from a much wider input spectrum in a process called down-conversion. The trend towards increased flexibility within this ‘front-end' part of the system is now allowing interoperability between different radio access technologies, permitting the dynamic reconfiguration of band-plans, and ‘future-proofing' the investment in receiver system design. Furthermore, ever increasing user demand for bandwidth coupled with new technologies such as MIMO (multiple input – multiple output), means that systems must be capable of supporting an increasing number of channels.
Until now, the approach has been to use specialist DDC ASIC-based devices that can typically handle up to four channels each. Thus a complex, multi-channel application requires numerous, large and expensive boards. RF Engines (RFEL), a specialist UK-based designer of signal processing solutions, has created a novel channelisation architecture that can handle up to 64 channels on a single FPGA device. This provides significant savings in terms of cost, space and power consumption, since one component can now replace up to sixteen ASIC devices, with savings becoming more significant as the number of channels increases.
Called ChannelCore64, the product utilises a unique approach to down-conversion that achieves massively greater silicon efficiency per channel than other FPGA-based DDC solutions, whilst providing all of the configuration controls that are typically associated with ASIC based DDCs. For example, the core fits comfortably within a Xilinx Virtex II Pro 30 FPGA device and consumes a maximum of 4W when all channels are active. Implementation in Altera devices provides equally impressive performance.
The core allows the user to independently select each channel from either of two input sources, tune the centre frequency and gain of each channel, and select from different filter shapes and bandwidths sample rates in order to adapt to a changing signal environment. An integrated high quality resampler ensures that an end-to-end dynamic range of at least 80dB is maintained even for fractional re-sampling ratios. This is significantly higher than for other comparable solutions with fractional re-sampling.
Eight independent user-programmable filter sets are supported, so that the user can specify the filters to match the required system performance. Possible filter designs include equiripple, root raised cosine, Gaussian, etc, depending on the application. The filter is designed at a high sample rate as part of the resampling process, but provides the equivalent of an 80-tap filter for a four-times oversampled output. The final filter shape is relative to the output sample rate such that each filter shape can provide a large number of possible output bandwidths.
The resampler provides an output rate control for each channel to allow matching with modulation symbol rates. Sample rates may be selected with a resolution of <0.01 Hz. Saturation level indication and fine-level gain control with 0.01dB resolution is provided for each channel, and all channels are completely independent from each other and can be reconfigured without interrupting the flow of other channels.
The key features of ChannelCore64 are:
ChannelCore64 is targeted at applications such as wireless base stations, satellite ground stations, and other multi-channel radio receivers. In these applications, MIMO can be used to great effect, i.e. by using additional antennas to obtain more signal information, these inputs can be processed to provide better quality reception by removing multipath effects and therefore a significantly improved quality of service. Traditionally, more antennas means more channels, which in turn would mean more ASICs, and therefore more costs and power consumption. However, using a ChannelCore64-based solution means that additional channels can be easily deployed, for example, going from 24 channels to 64, providing significantly better quality performance for negligible incremental costs. ChannelCore64 is delivered as an EDIF netlist with user constraints file, instantiation template, VHDL model and Test Bench and Matlab model. The bit-true Matlab model is available free of charge and allows designers to accurately simulate ChannelCore64 within their system context. The core is supplied under a simple licensing model, and custom variants, including up-converters, can be produced on request. ChannelCore64 has been fully tested to provide a rapid, low risk solution that has been optimised for use in these applications as opposed to general purpose cores, which are designed for a wide range of applications and therefore are not as efficient in terms of performance or FPGA area.
This 64 channel version of the core is matched to state-of-the-art ADC technology and is intended to provide generic functionality to meet the broadest possible set of requirements. However, RFEL specialise in custom FPGA development and are able to quickly provide alternative variants of the core tailored to specific requirements. The major parameters that can be varied for a given realisation of the core include: data and programming interfaces, frequency and rate precision, filter parameters and spurious free dynamic range.
Further Information please contact:
RF Engines Limited Web: www.rfel.com Email: info@rfel.com Tel: +44 (0)1983 550330
ChannelCore64 is a trademark of RF Engines Limited |
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