 |
Use a Mix of FPGAs and DSPs in Wireless Basestations For Cost-Effectiveness and Market Agility
By Deepak Boppana, Altera Corp.
“Intelligent partitioning” between FPGAs and DSPs allows wireless systems designers an optimal combination of features and cost-effectiveness. Currently there is no “one fits all” design solution. Applying a mix of DSPs and FPGAs brings future proofing as well as risk-free cost-reduction benefits. System partitioning combining programmable logic with DSPs for wireless basestations leads to greater design and market success. The need for higher data rates are driving the evolution of wireless cellular systems from narrowband 2G GSM, IS-95 systems to current-generation W-CDMA-based 3G and 3.5G systems supporting peak data rates up to 10 Mbps. Future 3GPP long-term evolution specifications point to complex signal processing techniques such as multiple-input multiple-output (MIMO) along with new radio technologies like orthogonal frequency-division multiple access (OFDMA) and multicarrier Code Division Multiple Access (MC-CDMA). These approaches will be key to achieving target throughputs in excess of 100 Mbps. Alternate OFDM-based broadband wireless systems such as WiMAX are now achieving transmission speeds in excess of 70 Mbps. This improvement in data rates has been enabled by higher order modulation techniques and variable rate channel coding. Complex spatial signal processing schemes including beam forming and MIMO antenna techniques are also paths to increasing data rates at the expense of additional hardware. However, these technologies create challenges for basestation designers requiring scalability, cost-effectiveness as well as flexibility across multiple evolving standards.
Multiple Moving Targets
Wireless systems designers need to meet a number of critical requirements including processing speed, flexibility, and time-to-market. These all ultimately drive hardware platform choices. The major variables include:
Logic Task Partitioning in the System Architecture Control, signal-processing and data path operations make up the bulk of the processing load in a wireless basestation. Most approaches accomplish these with combinations of microcontrollers (MCUs), FPGAs and programmable DSPs. The MCU controls the system, while the FPGA and DSP handle the data-flow processing. Systems with light processing demands and control-oriented tasks are implemented in software on a DSP; heavier loads are best implemented in FPGAs with their significant parallel processing abilities. Combining DSPs and FPGAs ensures complete system flexibility and offers reprogrammability to fix bugs or even support different standards. Partitioning strategy between FPGAs and DSPs depends on processing requirements; system bandwidth as well as system configuration; and the number of transmit and receive antennas. Figure 1 shows a typical DSP/FPGA partitioning for baseband physical layer (PHY) functions in an OFDMA-based system such as WiMAX or LTE.
Figure 1: DSP/FPGA partitioning for OFDMA systems By incorporating advanced multiple antenna technologies, the throughput offered by such systems is expected to be between 75-100Mps. The baseband PHY functionality can be broadly categorized into bit-level processing and symbol-level processing functions. Following is an overview of these functions and how FPGAs are used to complement DSPs for implementing both bit-level and symbol-level functions. Bit-Level Processing The bit-level blocks include randomization, forward error correction (FEC), interleaving, and mapping to quadrature phase shift keying (QPSK) and quadrature amplitude modulation (QAM) functions on the transmit side. The corresponding receive processing bit-level blocks are symbol de-mapping, de-interleaving, FEC decoding, and de-randomization. All bit-level functions except FEC decoding are relatively straightforward and not computationally intensive. For example, randomization involves modulo-2 addition of the data bits with the output of a simple pseudo-random binary sequence generator. Although FPGAs offer more flexibility for bit-level manipulations than DSPs with fixed bus widths, the low computational complexity allows DSPs to manage these functions. Conversely, FEC decoding—including Viterbi decoding, Turbo convolutional decoding, Turbo product decoding, and LDPC decoding—are computationally intensive and consume significant bandwidth when done with DSPs. FPGAs are widely used to offload these functions and free DSP bandwidth for other functions. The same FPGA can also be used to interface to the MAC layer as well as implement certain lower MAC functions such as encryption/decryption and authentication. For example, Altera's low-cost Cyclone™ II FPGAs are suited to such DSP co-processing functions. Symbol-Level Processing Symbol-level functions in OFDMA systems include sub-channelization and de-sub-channelization, channel estimation, equalization and cyclic prefix insertion, and removal functions. The time-to-frequency domain conversion and vice-versa are implemented using FFT and IFFT, respectively. Channel estimation and equalization can be performed offline and involve more control-oriented algorithms that are better suited for DSPs. Conversely, FFT and IFFT functions are regular data path functions involving complex multiplications at very high speeds and are better suited for implementation on FPGAs. Figure 2 shows the embedded DSP blocks contained in a high-end FPGA (Altera® Stratix® II device). DSP processors typically have up to eight dedicated multipliers, whereas Stratix II devices offer up to 384 18x18 dedicated multipliers providing throughputs of up to 346 GMACs, an order of magnitude higher than currently available DSPs.
Figure 2: Embedded DSP blocks in FPGAs Such a massive difference in signal processing capability between FPGAs and DSPs is further accentuated when dealing with basestations employing advanced, multiple antenna techniques such as space time coding (STC), beamforming, and MIMO schemes. The combination of OFDM-MIMO is widely regarded as a key enabler of higher data rates in current and future WiMAX and LTE wireless systems. Figure 1 shows multiple transmit and receive antennas employed at a basestation. In this configuration, symbol processing functions are implemented separately for each antenna stream before MIMO decoding is performed, producing a single bit-level data stream. The symbol-level complexity grows linearly with the number of antennas when implemented on DSPs that perform operations in a serial manner. For example, when two transmit and two receive antennas are used, the FFT and IFFT functions consume approximately 60 percent of a 1GHz DSP when the transform size is assumed to be 2048 points. In contrast, a multiple antenna-based implementation scales very efficiently when implemented with FPGAs. FPGAs provide parallel processing and time-multiplexing between the data from multiple antennas. The same 2x2 antenna FFT/IFFT configuration can be implemented using less than five percent of an Altera Stratix II 2S180 FPGA. Multiple antenna schemes provide higher data rates, array gain, diversity gain, and co-channel interference suppression. Beamforming and spatial multiplexing MIMO techniques are also computationally intensive, involving matrix decompositions and multiplications. Specifically, Cholesky decomposition, QR decomposition, and singular value decomposition functions are useful in solving the linear set of equations common in these systems. While these functions quickly exhaust DSP capabilities, they are well suited for FPGAs using well known systolic array architectures that provide a more cost-effective solution by exploiting FPGA parallelism. Digital IF Processing
Figure 3 shows data from a baseband channel card being sent to a RF card for subsequent digital intermediate frequency (IF) processing, including digital up-conversion (DUC), crest factor reduction (CFR), and digital predistortion (DPD). Digital IF extends the scope of digital signal processing beyond the baseband domain to the antenna—to the RF domain. This increases the flexibility of the system while reducing manufacturing costs. Moreover, digital frequency conversion provides greater flexibility and higher performance (in terms of attenuation and selectivity) than traditional analog techniques. CFR and DPD functions are required to improve the efficiency of power amplifiers used in basestations. These functions also help to significantly reduce the total cost of the RF card. Both CFR and DPD involve complex multiplications at sample rates as high as 100+Msps. Similar to DUC, digital down-conversion (DDC) is required on the receive side to bring the IF frequency down to baseband. Both DUC and DDC use complex filter architectures including finite impulse response (FIR) and cascaded integrator-comb (CIC) filters. Advanced FPGAs provide hundreds of 18x18 multipliers running at speeds as high as 350-MHz. Not only does this provide a platform capable of processing multiple channels in parallel, it also yields a cost-effective, integrated single-chip solution.
Figure 3. Digital IF Processing Functions
Conclusion
As standards stabilize, the initial need for flexibility in basestations should subside while cost becomes a major success factor. Choosing FPGAs that have a risk-free migration path to low-cost structured ASIC technology will enable significant cost savings. As an example Altera's HardCopy® II technology provides a seamless, risk free migration path from Stratix II FPGAs to significantly lower cost HardCopy II Structured ASICs, while also increasing system performance and decreasing power consumption.
Hybrid FPGA/DSP based platforms provide an effective design approach for wireless basestations. What's essential to product success is intelligent partitioning between the FPGA and DSP based on system throughput requirements and long-term cost considerations. This will ensure final products that are not only scalable and cost-effective, but flexible and reconfigurable across multiple evolving standards.
Deepak Boppana is a technical marketing engineer with Altera's wireless business unit. He is responsible for communicating efficient system design techniques and architectures for wireless applications to the company's customers. He joined Altera in 2003 and has over five year's experience in wireless communications system design and implementation. He has been published in research publications, international conferences and technical journals. He holds a BSEE from the University College of Engineering-Osmania University, and a MSEE from |
|
