A cost-effective SDR platform for multi-antenna 802.16e infrastructure

By Jeremy Hendy – VP Marketing, Aspex Semiconductor

As the WiMAX industry starts to deploy first-generation 802.16d WiMAX networks, many infrastructure vendors are planning the development of their next-generation platforms, to be launched in 2006/2007, with support for the emerging 802.16e standard. 

Different vendors are targeting a very wide range of applications, from cost-effective single-antenna applications, through to ultra high-performance Adaptive Antenna Systems (AAS) and Multiple Input, Multiple Output (MIMO) implementations for city-wide broadband wireless access.

Despite these wildly differing requirements, a common set of vendor requirements can be identified for the critical Physical Layer (PHY) platform:

1. The need for futureproof, software-defined platforms to support future evolutions of the 802.16 standard;

2. The desire to add value through proprietary AAS/MIMO algorithms, rather than building “me-too” products.

3. Lower cost-per-equivalent-sector;

4. The need for scalable, modular technologies which are not constrained to any particular modulation scheme;

Aspex has recently launched an 802.16d/e PHY solution for 802.16e infrastructure, based around the Linedancer family of chips, which incorporate our unique ASProCore parallel processing technology. 

Using Linedancer, vendors can deploy a fully software-defined-radio solution, confident that it can be updated in the field to accommodate new standards and innovations.  A single Linedancer device can support multiple sectors with up to 8 antennas per chip, allowing vendors to develop flexible and cost-effective SDR solutions.

The parallelism of ASProCore allows Linedancer to support 4-antenna sectors with an overhead as low as 10% when compared to single-antenna implementations.

ASProCore technology

ASProCore is a parallel processing DSP technology which integrates many thousands of small, software-programmable processing elements in a single chip. 

Unlike most other parallel or array-processing solutions, all of our processing elements act as a single co-processor to an on-chip RISC CPU, dramatically simplifying the programming model.

And because all the processing elements are connected in a one-dimensional string, it is easy to cascade multiple chips together to achieve whatever performance is needed, with no complex software partitioning or synchronisation to worry about.

Each processing element implements user-defined arithmetic precision on an operation-by-operation basis, allowing algorithm designers to trade off precision with performance on a fine-grain basis.

Linedancer chips are fully software programmable, using a straightforward C-based compiler toolchain.  As the chips contain no 802.16e specific hardware, vendors can be confident that the platform provides a futureproof, scalable solution for PHY processing.

802.16e Multi-antenna combining

The OFDM modulation scheme used in 802.16 is naturally parallel, with up to 2,048 subcarriers used in every symbol.  AAS and MIMO bring yet more parallelism to the system, making ASProCore an ideal fit to the application.

A high-speed inter-processor communication network allows processing elements to share information with bandwidths of up to 3.2 terabits/second, making antenna combining simple and cheap to implement.

Taking the FFT task as an example, each ASProCore processing element can be used to perform one butterfly of the FFT.  With 4,096 Processing Elements per chip, this allows us to execute up to 8,192 FFT points in parallel. When operating in OFDM-256 mode, we can therefore process 32 symbols of information at the same time.

These 32 symbols could be allocated to a single antenna, or could be distributed amongst multiple antennas as illustrated in the diagram.  When used for multiple antennas, the array contains information about both space and time, making MIMO channel estimation and correction algorithms convenient and straightforward to implement.

The 256-point FFT executes in just 10 microseconds, giving an aggregate rate of up to 3.2 million FFTs/second.  For a single antenna 5 MHz sector, this FFT task equates to less than 2% of the available processing power of a Linedancer chip.

An additional benefit to the parallel approach is that the channel correction takes place in parallel, allowing weights to be applied on a per-antenna, per-user, or per-subcarrier basis at no extra cost, giving infrastructure vendors the freedom to develop a wide range of AAS/MIMO algorithms.

Matlab system modelling environment

For fast time-to-market, Aspex has worked with Cambridge Consultants to develop a Matlab system modeling environment, based around Aspex's Accelera PCI-X plug-in card.  This allows algorithm developers to develop complex subscriber and channel models in the familiar Matlab environment, with Aspex's 802.16 PHY code executing in real-time on the Accelera card's Linedancer processors.

Unlike traditional modelling environments, this “hardware in-the-loop” approach allows algorithm designers to instantly see the effects of system tradeoffs on performance.  As the PHY algorithms are running in real-time on the final target platform, there is no time-consuming validation or co-simulation step to ensure that the simulation model matches the final implementation.

802.16 PHY reference code

Aspex has developed a suite of 802.16 PHY reference code to provide infrastructure vendors with a starting point for product development.  Available as source, the reference code allows vendors to add value through customisation, and implementation of proprietary channel estimation algorithms.

Summary

Aspex's Linedancer platform takes advantage of the natural parallelism of 802.16e multi-antenna OFDM modulation and demodulation to provide a cost-effective Software Defined Radio solution for advanced WiMAX architecture.

Like DSP technology, Linedancer is fully software-programmable, giving fast time-to-market and a futureproof environment, but provides significantly higher performance for demanding infrastructure applications and cost-effective multi-sector products.

With open access to reference code, and an integrated Matlab development environment, the platform provides infrastructure vendors with a fast-track route to develop high performance, differentiated solutions for 802.16e and beyond.

Jeremy Hendy joined Aspex in 2004 as Vice President of Marketing. 

Previously, Jeremy was Strategic Technology Director of Cadence's Wireless and Multimedia Design Services team headquarted in Cambridge, UK, with responsibility for product development and Intellectual Property licensing for technologies such as 3G, Bluetooth, 802.11 and DVB-T.  Prior to joining Cadence, Jeremy had spent 7 years with UK wireless systems design house Symbionics, and 4 years with Texas Instruments' wireless applications group. 

Jeremy can be contacted at jeremy.hendy@aspex-semi.com