Having been active within the Open Basestation Architecture Initiative (OBSAI) from the beginning, using their Stratix GX family of advanced FPGAs, Altera became the first FPGA vendor in December 2003 to support the Reference Point 3 (RP3) Baseband to RF module interface specification.

The original aim was to develop a reference design, demonstrating the integration of the link-layer function together with the physical layer (See Fig (1)) within a single StratixGX™ device. The demonstrator also enabled Altera to provide constructive feedback to the RP3 working group, as the specification was forged.

StratixGX™ integrates 3.125Gbps transceivers onto the highly successful Stratix FPGA architecture. The transceiver implementation provides Clock Data Recovery, SERDES, 8b/10b encoder/decoder, pattern detector and word aligner, all of which are used to provide the Physical Layer implementation of the OBSAI specification. These dedicated blocks both simplify system design and leave the FPGA available to support upper layers of the specification and custom system architecture.

For the link layer reference design, Altera made use of the configurable logic resources of the Stratix GX device. The Transmission Link interface is relatively simple and consists of the RP3 framer, transmit link state machine. The framer simply takes 8bit data and coverts into RP3 CDMA/WCDMA ready for transmission through the physical layer. The transmit link state machine is responsible for establishing the link and then ensuring successful data transfer between the Transport Layer and the Physical layer, once the data is correctly framed.

The Receiver Link Interface consists of receiver synchronization state machine, frame checker & Alignment checker. This block ensures initialisation on receipt of the correct number of idle characters (K28.7) from the transmitter. Once the link is synchronized, the block passes the recovered data to the Transport layer providing any error counts are within the RP3 guidelines. The block is also responsible for reporting error count and status flags.

The RP3 reference design enabled Altera to demonstrate data recovery over a far more stressful channel model than that called for in the specification. See fig(x).. Signal Integrity is imperative at higher data edge rates, because losses across transmission mediums such as FR4 PCB fabric cause a deterioration of high frequency signal. The Stratix GX transceiver includes dynamically controllable pre-emphasis & receiver equalisation, which are used to compensate for signal losses, and therefore maintains signal integrity. By employing these techniques, Altera were able to run a BER (Bit Error Rate) test of 10 -15 without any errors

The Altera RP3 Reference design provides customers with a flexible solution for meeting the OBSAI RP3 specification. In total, the link layer consumed only a small amount of the available configurable logic and memory resources so that further integration of other radio card functions such as digital up/down conversion (DDC / DUC) and digital pre-distortion functions is possible. Stratix GX family provides a number of different Logic and Transceiver configurations. The family is suited to a variety of applications from single channel RF Modules to multi channel Basestation Modules.