BiCom3 SiGe High-Speed Semiconductor Process Enables New Breed of High-Performance Analog Components
By Matthias Feulner, Texas Instruments Business Development Manager, Wireless Infrastructure BiCom3 Process Technology and its MeritsThe BiCom3 is an advanced high-performance complementary Bi-CMOS process that lends itself very well to the design of high-speed components, boasting high transistor transit frequency, but at the same time also high linearity and precision. Since the process was built on the basis of a prior-generation digital process library, it comes with a full suite of digital components and thus allows for integration of digital logic next to bipolar circuit structures, enabling implementation of more complex functions. Recent breakthroughs in devices aimed at wireless communications, medical imaging and high-end test & measurement demonstrate this process' potential for high-speed component design. We will highlight the differentiating features of the process itself, explain how they relate to certain device performance parameters and review the results on some real components. SiGe and Transit Frequency fTDoping a transistors base region with silicon-germanium (SiGe) allows a reduction in base transit time while maintaining a high b*VA product of > 10,000, a measure of transistor linearity. With that current instances of the BiCom3 deliver transit frequencies of up to 18GHz for both NPN and PNP transistors, which is remarkable since many high-speed processes are optimized to achieve top speed for NPN transistors only and provides about twice the speed of the fastest comparable high-speed process. As a result, truly complementary architectures are possible, which in turn is a key enabler for designing high-speed analog circuits. SOI Technology and DistortionThe BiCom3 process employs silicon-on-insulator (SOI), separating the top active silicon from the support substrate with a buried oxide (BOX), greatly reducing parasitic capacitances and resulting in very high current-gain early-voltage product b*VA of > 10000, a measure of linearity for transistors, which is about four times as high as the closest comparable high-speed process..
These two features, speed and linearity, in combination do put the BiCom3 process in comparison with other existing high-speed processes into a spot that's far ahead in both categories as can be seen from below comparison chart.
NiCrAl Thin-Film ResistorsImplementation of thin-film resistors in the process is adding the precision feature to high-speed. While the un-trimmed resistors already allow for excellent ratio matching with 0.1% accuracy, laser-trimming yields up to a factor 100 improvement, positively impacting properties like for example input offset voltage. High-Performance ADC Implemented in BiCom3The combination of high-speed and high linearity seems to fit almost perfectly for a high-speed data converter with low signal distortion. The sample-and-hold input stage and the signal path as a whole benefit greatly from the high bandwidth delivered by the process while subsequent conversion stages in a pipeline architecture take advantage of the high-linearity properties, resulting in very low harmonic distortion.
What's more, the process' low-distortion properties allow the implementation of an input buffer before the sample-and-hold stage without degrading performance (which would not be possible in CMOS converters).
Figure 2: Sample and hold with input buffer
It's just this input buffer architecture that reduces spikes on the input signal caused otherwise by switching of the sample-and-hold's sampling capacitor. This in turn is the main reason for the device's constantly good SFDR over a broad input frequency range.
The results are demonstrated looking at Texas Instruments' ADS5424, a new analog-to-digital converter implemented in BiCOM3. Spurious-Free Dynamic Range and Signal-to-Noise RatioFrom considerations above, the low-noise and high-linearity properties of the BiCOM3 process should be reflected in the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) of the converter. To verify this we have measured and plotted performance of the converter at various sampling rates popular for in 3rd generation wireless base stations.
Figure 3: ADS 5424 Singal-to-Noise ratio vs. input signal frequency
Figure 4: ADS 5424 Spurious-Free-Dynamic-Range vs. input signal frequency
Both SNR and SFDR plots indicate that the device delivers excellent performance for base-band as well as intermediate frequency (IF) sampling applications up to >200MHz input frequency . Challenges in Achieving Optimum Performance
But the maximum performance of such top-notch AD converter is not readily available. On the contrary there are many degrading factors that may result in sub-optimum performance if not addressed properly and thus the design challenge is not restricted to the analog-digital converter alone. We'll pay attention to the most critical ones, namely ADC clock jitter, driver op amp noise and harmonic distortion, analyzing the impact and suggesting adequate resolutions.
Degradation through Clock Jitter
Clock jitter is a major concern particularly when sampling at high input frequencies. Below figure shows dependence of theoretically achievable SNR of an AD converter on jitter (total jitter being the combination of the ADC's aperture jitter and the clock jitter, the latter one assumed to be dominant):
Figure 5: Dependence of theoretically achievable ADC SNR on jitter
A look at the plot above readily shows that achieving the maximum SNR of around 74dB at 100MHz input frequency and 92MSPS sampling rate will require sub-ps clock jitter (assuming that the ADC aperture jitter is minimized by design). Since many systems are distributing the reference clock via backplane or another connection that degrades the signal quality, usually a local oscillator (a low phase noise VCXO) serves as the timing source for the ADC. An implementation using the CDC7005 clock synchronizer from TI with a low-noise VXCO provides clock jitter (represented by phase noise plot below where timing jitter is phase noise integrated over a certain frequency band) as low as only a few 100fs, overcoming this bottle-neck for the ADC's SNR performance.
Figure 6: CDC7005 clocking AD converter
Figure 7: Phase noise diagram for ADC clock tree
Degradations Caused by Op Amps
While above example demonstrates that BiCom3 based ADCs can deliver exceptional performance, what is it worth if the op amp driving the ADC doesn't match in performance and thus becomes itself the limiting factor for distortion and noise performance? There are a number of reasonably good driver op amps for low signal frequencies, but the real challenge becomes apparent with IF sampling ADC configurations where most amplifiers show significant degradation in harmonic distortion.
Obviously careful selection of the right amplifier is critical to overall performance. We'll again use the practical example of the ADS5424 at 100MHz IF and 92.16MSPS sampling rate, a typical configuration used in 3G wireless communications. The ADC itself could deliver SNR of 74dB and SFDR of 87dBc. Matching this with a similarly performing op amp is very challenging and thus often transformers are used as a backup, but now BiCom3 based amplifiers take performance to the next level.
High-Performance Op Amp Implemented in BiCom3Harmonic DistortionSeveral BiCOM3 features outlined earlier do contribute to exceptionally low harmonic distortion properties:
Figure 8: THS4509 harmonic distortion in comparison
As a result 2nd and 3rd harmonic with the THS4509 as plotted above can be plainly characterized exceptional maintaining more than 10dB improvement over previously available devices over a very wide frequency range. Noise Contribution
The noise performance of an op amp is dominated by 1/f noise at low frequencies and by white noise at higher frequencies which depend on the process itself and current density Jc. The chart below shows the resulting noise behavior for the THS4509, effectively delivering 25% lower noise than previously available op amps.
Figure 9: THS4509 noise characteristics High-Performance Receiver Solution
Figure 10: Receiver circuit implementation
Applying the above mentioned devices in a receiver circuit is the ideal way to demonstrate the outstanding performance available with BiCOM3 and the components designed with it. We take a look at SNR and SFDR, the measures for a receiver's sensitivity and its ability to detect very small signals in the presence of larger ones
Figure 11: Measured SNR / SFDR for THS4509 + ADS5424 combination
Both SNR and SFDR plots for the THS4509/ADS5424 combination show excellent performance across a very wide input signal frequency range from base band up to far beyond 50MHz, demonstrating the merits of these BiCom3 designed devices.
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